Flow for vector capture

ABSTRACT

A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence. An overlay is performed on the two sequences to enable generation of the synchronous sequence of vectors for verifying operations of an IC design by a tester.

TECHNICAL FIELD

The invention relates generally to the verification and testing ofelectrical circuits and more particularly to a method and system forgenerating synchronous test vectors from information originating withinan asynchronous environment.

BACKGROUND ART

An important phase in integrated circuit (IC) chip design andmanufacturing involves implementing a software verification tool tosubstantiate the functionality of a prototype design prior tofabrication. Chip parameters are specified and are modeled utilizing ahigh-level hardware description language (HDL), such as Verilog, VHDL,or C functions, to describe the IC at a higher level of abstraction thangates or transistors. Verifying the operations of the prototype prior tofabrication ensures that the requirements defined by the chipspecifications are satisfied, from layout to electrical parameters. Inparticular, the verification process provides feedback to the engineers,so that any detected defects can be corrected. This is potentiallycritical, since eliminating problems at an early stage results insubstantial savings in the time and cost of manufacturing.

Typically, the HDL simulation can be divided into a functional analysisand a timing analysis. The functional analysis verifies that the designlogic performs as intended (i.e., whether the chip will work or not) inan “event-driven” asynchronous environment in which informationregarding timing is not considered. Each internal component may beassumed to include a given time delay. Alternatively, an output statemay incur a timing delay that is different from that of a next outputstate. Simulated test signals propagate from an input end to an outputend of the design to provide output signals that are subsequentlycompared with predetermined target signals (i.e., anticipated referencesignals). Based on any unexpected outputs, design parameters aremodified when necessary.

Independent of the functional analysis, the timing analysis focuses onwhether the design logic operates within time constraints. This isimportant, since the prototype must be made compatible with otherdevices. A timing margin is generated based on factors such as thephysical characteristics of the design, including lengths of internaltransmission lines and bus specifications. Timing parameters, includingpropagation delay, strobe time, and setup and hold times are considered.

Data from both the functional analysis and the timing analysis iscaptured. The captured data may be used by an automatic test generator(ATG) to create test vector files of state data for subsequent physicaltesting of a device under test (DUT) that is fabricated based on theprototype design. The testing is typically performed by a conventional“time-driven” ATG operating in a synchronous environment in which datais sampled at a predetermined fixed instance in every successive testercycle.

A concern is that there may be at least one occasion of an inability ofthe synchronous tester to properly sample DUT data as a result of anasynchronous variability of data from the DUT. Since the tester isconfigured to sample data at predetermined instances in successivetester cycles while operating in the synchronous environment, the testeris not well adapted for sampling incoming data from the DUT that changesstates at unpredictable times due to its asynchronous behavior. This isproblematic, because if the timing margin of the DUT does not include asufficient time period before and after an active tester edge (i.e.,T_(setup) and T_(hold)) needed by the tester for sampling the outputdata from the DUT, the tester may exhibit responses that are differentfrom those generated during test simulation. Consequently, the testvectors produced by the ATG based on the simulated data may not triggerthe intended behavior within the asynchronous prototype design. Properlyidentifying the precise placement of the active tester edges for datasampling is often iteration intensive. That is, in attempting to fix theplacement of a tester edge to correspond to a sampling instance, thelocation is often determined by probing one instance after another untilan adequate timing is found.

What is needed is a method for test data generation in which timingvariability from an asynchronous device can be properly sampled by asynchronous tester.

SUMMARY OF THE INVENTION

The Invention is a method and system for generating a synchronoussequence of test vectors from information originating within anasynchronous environment. In a first sequence-generating step, asimulation synchronous sequence of states for functionally verifyingproper operations of a simulated Integrated circuit (IC) design Isprovided in a system simulation device (i.e., an IC design tester). Thesequence is generated from a simulated asynchronous sequence byextracting a state of the simulated asynchronous sequence at each clockperiod of a reference clock. Preferably, the reference clock period isequivalent to a tester clock period. Abbreviated system-related delays(which may be “best case” delays encountered within the intended systemin which the IC is to be integrated) and extended system-related delays(which may be “worst case” delays encountered within the intendedsystem) are preferably considered in this first sequence-generatingstep.

In a second sequence-generating step, the simulation synchronoussequence is manipulated once to include potentially different shorttiming delays for generating an asynchronous short-delay sequence and ismanipulated a second time to include potentially different long timingdelays for generating an asynchronous long-delay sequence. The shorttiming delays and the long timing delays are delays associated with thetester IC being simulated. Similar to the system-related delays of thefirst step, these short and long delays may be individually determinedon the basis of “best case” (minimum) and “worst case” (maximum) timerequirements, but these time requirements are related to either or bothof the IC and the tester, rather than to the intended system.

As a preliminary to a third sequence-generating step, separate timingoverlays are performed among the clock periods of the asynchronousshort-delay sequence and among the clock periods of the asynchronouslong-delay sequence to respectively identify a first state overlappingtime interval and a second state overlapping time interval. Each state“overlapping” time interval is that region of the cumulative clockperiod that includes at least a portion of the state of every clockperiod that is “overlaid” (i.e., time aligned) to form the cumulativeclock period. Within the third step, a clock period having a state withthe timing characteristics of the first state overlapping time intervalwithin its cumulative clock period is duplicated in a succession ofclock periods to generate a synchronous short-delay sequence. In thesame manner, a clock period having a state with the timingcharacteristics of the second state overlapping time interval within itscumulative clock period is duplicated within a succession of clockperiods to generate a synchronous long-delay sequence.

Finally, in a fourth sequence-generating step, a combined timing overlayis performed on the synchronous short-delay and long-delay sequences toprovide a single stream of sampling time intervals that defines thesynchronous sequence of test vectors for testing the IC design.

Returning to the first sequence-generating step, the original simulatedasynchronous sequence of states is created for verifying thefunctionality of a prototype design of an IC chip without anyconsideration of timing constraints. The asynchronous sequence isevent-driven and non-periodic (i.e., a timing delay of a first state maybe different from a timing delay of a next state). As previously noted,the asynchronous sequence is synchronized by extracting a state at eachclock period to generate the simulated synchronous sequence of states.The clock period preferably reflects the tester clock period of the ICdesign tester.

As a component of the first step, the timing constraints that areimposed by the intended system are considered. The abbreviated (minimum)and extended (maximum) system-related delays of the anticipated systemenvironment are independently introduced to the simulated synchronoussequence of states to respectively generate a simulated synchronousabbreviated-delay sequence of states and a simulated synchronousextended-delay sequence of states. The timing delays of the systemenvironment are indicative of the load characteristics of the componentswithin the intended system. As an example of an application, theintended system may be a laser printer. In one embodiment, theabbreviated-delay sequence represents the best case scenario, or minimumtiming delays, of the components within the system in which the IC willbe operating, excluding any delay associated with the IC itself and withthe IC design tester. Similarly, the extended-delay sequence representsthe worst case scenario, or maximum timing delays, of the componentswithin the system environment, excluding delays associated with the ICand the IC design tester.

Also within the first sequence-generating step, a first time overlay isperformed. The time periods of the simulated synchronousabbreviated-delay sequence and the simulated synchronous extended-delaysequence are time-aligned to identify a stream of intersecting timingregions (or “overlapping time intervals”) between corresponding statesof the two sequences in order to define the simulation synchronoussequence that is used in the second step. In a case in which there isnot an acceptable number of intersecting timing regions for defining anoperable simulation synchronous sequence, the simulated synchronousextended-delay sequence is adapted to be the simulation synchronoussequence to be used. In one embodiment, there is an unacceptable numberof intersecting timing regions in a case when there is no intersectingtiming region upon performing the time overlay on the two sequences.

Turning to the second sequence-generating step, the simulationsynchronous sequence from the first step is independently executed toinclude short timing delays for generating the asynchronous short-delaysequence and long timing delays for generating the asynchronouslong-delay sequence. In one embodiment, the short timing delays includea best case tester-load timing delay of the tester and a best casechip-load timing delay of the IC. Each tester-load timing delay is theinternal delay of the tester for a particular event, including delaythat results from capacitances and resistances that are associated withthe tester's circuitry and connections. The values of the delays may beprovided by the manufacturer of the tester. The chip-load timing delayis the internal delay of a fabricated chip based on the simulated ICdesign, with the value of the delay closely approximating theanticipated delay of the fabricated chip. Since the chip is designed toperform different types of functions in which the times taken to performdifferent functions vary, the timing delay associated with a firstoutput state may be different from that of a second and subsequentoutput state. The change in timing delay between the different outputstates is the basis for the asynchronous variability exhibited by thechip. Thus, the generated asynchronous short-delay and long-delaysequences are subjected to asynchronous variability. In a case in whicha delay has caused a state to cross a boundary into a next clock period,the sequence may be shifted along the time domain so that at least aportion of the crossed-over state is shifted back to its respectiveclock period. Alternatively, the crossed-over state may be masked toavoid a faulty sampling region.

As previously described, a time overlay is performed among the timeperiods of the asynchronous short-delay sequence to identify a firstoverlapping time interval. The overlaying includes correlatingsuccessive clock periods (with the differences in delays remainingintact) and identifying an intersecting time interval (i.e., region ofcoincidence) among the states of the cumulative period. In an event inwhich a state does not coincide with the overlapping time interval, thenon-overlapping time interval may be masked. The first overlapping timeinterval is duplicated by positioning the interval at a substantiallyidentical location in successive clock periods to generate thesynchronous short-delay sequence.

Independent of identifying the first overlapping time interval, a secondoverlapping time interval is identified. A time overlay is performedamong the time periods of the asynchronous long-delay sequence toidentify the second overlapping time interval of states. In an event inwhich a state does not coincide with the overlapping time interval, thenon-overlapping time interval may be masked. The overlaying includescorrelating successive clock periods and identifying an intersectingtime interval among the states of the cumulative period. The secondoverlapping time interval is duplicated by positioning the interval at asubstantially identical location in successive clock periods to generatethe synchronous long-delay sequence.

In the final sequence-generating step, a sequence-to-sequence overlay isperformed. The synchronous short-delay sequence and the synchronouslong-delay sequence are time-aligned to determine a stream of samplingtime intervals between corresponding states of the synchronousshort-delay and long-delay sequences. The stream of sampling timeintervals defines the sequence of synchronous test vectors.

A sampling instance is selected at a timing location within the samplingtime interval to correspond to a rising edge of a tester clock cycle ofthe IC design tester. The selection of the sampling instance includesallocating a sufficient time interval (i.e., T_(setup)) before thesampling instance and a sufficient time interval (i.e., T_(hold)) afterthe sampling instance, but within the sampling time interval, to ensurean adequate sampling of the vector by the tester. Since the sequence ofsampling time intervals for defining the sequence of test vectors issynchronous, the selection of the location of the sampling instance inone sampling time interval will be repeated for each sampling timeinterval in the synchronous sequence of test vectors.

The synchronous sequence of test vectors is executed to accommodate theshort timing delays and the long timing delays for verifying timingcorrectness. In the embodiment in which the short timing delays includethe best case tester-load timing delay and the best case chip-loadtiming delay, and the long timing delays include the worst casetester-load timing delay and the worst case chip-load timing delay, thesequence is verified to ensure that the vectors from the simulated ICcan be adequately sampled by the tester within a testing environmentthat includes timing delays occurring from all of the system, the chipand the tester.

An advantage of the invention is that the sampling time interval thatdefines the test vector can be determined without the cumbersome andtime consuming task of probing one location after another to find anadequate sampling instance. Moreover, detailed knowledge relating to thetiming delays of every low-level circuit within the testing environmentis not required. Thus, the invention allows for a quick convergence ofthe sampling time intervals within the synchronous sequence of testvectors. Another advantage is that since the synchronous sequence oftest vectors has been verified against the testing environment, errorsresulting from sampling at undesired locations can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a process flow diagram for generating a simulation synchronoussequence of states from information originating within an asynchronousenvironment in accordance with the invention.

FIG. 2A is a timing diagram illustrating the timing relationship forgenerating a simulated synchronous sequence in accordance with theprocess flow diagram of FIG. 1.

FIG. 2B is a timing diagram illustrating the timing relationship forgenerating a simulation synchronous sequence in accordance with theprocess flow diagram of FIG. 1

FIG. 3 is a process flow diagram for generating a synchronous sequenceof test vectors in accordance with the invention.

FIG. 4 is a timing diagram illustrating the timing relationship forgenerating a synchronous short-delay and long-delay sequences inaccordance with the process flow diagram of FIG. 3.

FIG. 5 is a timing diagram illustrating the timing relationship forgenerating the synchronous sequence of test vectors in accordance withthe process flow diagram of FIG. 3.

FIG. 6 is an expanded view of an overlaid cycle of the synchronoussequence of test vectors of FIG. 5 having a selected sampling instance.

FIG. 7 is a block diagram of a system that is configured to generate thesynchronous sequence of test vectors of FIG. 3.

FIG. 8 is a block diagram of the system of FIG. 7 that is configured togenerate the synchronous sequence of test vectors.

DETAILED DESCRIPTION

The method and system for generating a synchronous sequence of testvectors comprises acquiring timing data from all of an intended systemenvironment, an IC design tester environment and an integrated circuit(IC) chip environment. The intended system is the one in which the IC isto be incorporated. For example, the intended system may be a laserprinter.

FIG. 1 shows a process flow diagram 10 for generating a simulation(synchronous) sequence of states from information originating within anasynchronous environment. In step 12, a simulated asynchronous sequenceof states for functionally verifying proper operations of a simulated ICdesign is provided under a system simulation environment. The simulatedasynchronous sequence determines that the internal components (e.g.,gates) of a simulated IC interact and function in the manner intended.In one embodiment, the simulated IC is an Application SpecificIntegrated Circuit (ASIC) to be incorporated as part of the systemenvironment. The system environment may be an operating environment of alaser printer having member devices such as ASICs, memories, drivers andcontrollers. A recording file, such as a Verilog Control Dump (VCD)file, captures the sequence and the timing information associated witheach transition of the sequence.

The simulated sequence is “asynchronous,” since the occurrences of thecycles containing state information is event-driven and non-periodic.That is, there is no timing constraint imposed upon the cycles. A timingdiagram 14 of FIG. 2A shows a partial exemplary simulated asynchronoussequence 16. The asynchronous sequence includes a first cycle 18 havinga first rising edge 20 at 5 ns and a first falling edge 22 at 25 ns, asecond cycle 24 having a second rising edge 26 at 50 ns and a secondfalling edge 28 at 70 ns, and a third cycle 30 having a third risingedge 32 at 85 ns and a third falling edge 34 at 105 ns. The non-periodicoccurrence of the cycles is shown by a difference of the time intervalsbetween adjacent cycles. In an exemplary case in which the rising edgeof each cycle is selected as a reference point, the time interval of 45ns between the first rising edge (at 5 ns) of the first cycle and thesecond rising edge (at 50 ns) of the second cycle is different from thetime interval of 35 ns between the second rising edge (at 50 ns) of thesecond cycle and the third rising edge (at 85 ns) of the third cycle.

Returning to FIG. 1, step 36 is a step of synchronizing the simulatedasynchronous sequence 16 to generate a simulated synchronous sequence ofstates. The asynchronous sequence can be synchronized by sequentiallyextracting a state of the asynchronous sequence at each periodic clock.FIG. 2A shows a reference clock 38 having successive cycles 40 inrespective base periods 42. Each base period comprises a time intervalthat is equivalent to a time interval of a next base period. Preferably,the time interval of the base period corresponds to the time interval ofa tester clock period of an IC design tester. In a sequential manner, byextracting a state of the asynchronous sequence 16 at each periodicclock, the states are phase-locked and time-aligned to an identicaltiming location in a base period to generate a simulated synchronoussequence 44 of states. Each cycle 46 of the synchronous sequencecoincides with the clock cycle 40 of the reference clock. Moreover, thetime period 48 of the synchronous sequence corresponds to the baseperiod 42 of the reference clock.

For each member device (e.g., a controller or a driver) operating withinthe intended system environment, there is a timing delay. Each memberdevice includes a best case timing delay and a worst case timing delay,resulting from a load variation inherent in the device. A best casetiming delay and a worst case timing delay of the system environment maybe acquired by adding respective best case timing delays and worst casetiming delays for every member device of the system.

In step 50 of FIG. 1, an abbreviated timing delay of the systemenvironment is introduced to the simulated synchronous sequence 44 ofFIG. 2A to generate a simulated synchronous sequence of states. In oneembodiment, the abbreviated delay is an estimated best case, or aminimum timing delay, of the system environment, excluding any delayassociated with the chip or the tester. However, the delay may beadjusted from the minimum in order to allow some error tolerance. FIG.2B shows a simulated synchronous abbreviated-delay sequence 52 having anexemplary timing delay 54 of 5 ns. By introducing the timing delay 54,each cycle 46 of the simulated synchronous sequence 44 is shifted alongthe time domain by 5 ns, resulting in the simulated synchronousabbreviated-delay sequence 52. The simulated synchronousabbreviated-delay sequence includes successive base periods havingshifted cycles 56.

Independent of introducing the abbreviated timing delay to the simulatedsynchronous sequence 44, step 58 of FIG. 1 introduces an extended timingdelay of the system environment to generate a second simulatedsynchronous sequence of states. In one embodiment, the extended delay isthe estimated worst case, or a maximum timing delay, of the systemenvironment, excluding any delay associated with the chip or the tester.However, there may be an error tolerance adjustment. FIG. 2B shows asimulated synchronous extended-delay sequence 60 having a timing delay62 of 10 ns. By introducing the timing delay, each cycle 46 of thesimulated synchronous sequence 44 of FIG. 2A is shifted along the timedomain by 10 ns, resulting in the simulated synchronous extended-delaysequence 60. The simulated synchronous extended-delay sequence includesrepeating shifted cycles 64.

In step 66 of FIG. 1, a time overlay is performed on the simulatedsynchronous abbreviated-delay sequence 52 and the simulated synchronousextended-delay sequence 60 to generate a simulation sequence 68 of FIG.2B. Specifically, the synchronous sequences 52 and 60 are time alignedand correlated to identify successive overlapping cycles 70 that definethe simulation sequence 68. The overlapping cycles are the coincidenttime interval between each cycle 56 and the cycle 64 within thecorresponding base period. The overlapping cycle is characterized by arising edge 72 that coincides with a rising edge of the cycle 64 (of thesequence 60) and by a falling edge 74 that coincides with a falling edgeof the cycle 56 (of the sequence 52). Since the overlaying is performedon synchronous sequences 52 and 60, the resulting simulation sequence isalso synchronous. In a case in which there is not an acceptable numberof overlapping cycles generated between the simulated synchronousabbreviated-delay and extended-delay sequences 52 and 60, theextended-delay sequence 60 is adapted to be the simulation sequence 68.In one embodiment, there is an unacceptable number of overlapping cyclesin a case when there is no intersecting timing region upon performingthe time overlay on the two sequences.

While the simulation sequence 68 provides successive synchronous timeintervals for data samplings, the intervals only include timing delaysassociated with the load characteristics of the system environment andnot any load characteristic associated with the tester and the IC chip.As a result, the simulation sequence may not be adequate in an actualtesting environment which must accounted for the tester and IC chip.

FIG. 3 shows a process flow diagram 80 for generating a synchronoussequence of test vectors from the simulation sequence 68 of FIG. 2B. Thesynchronous sequence of test vectors includes timing delays associatedwith the tester and the IC chip.

The tester-load timing delay is considered in isolation from any timingdelays associated with the system and the chip. The tester delayincludes delays resulting from the load impedance of the device. Thereis a best case, or a minimum timing delay, and a worst case, or amaximum timing delay, associated with a load variation inherent withinthe tester. That is, even with a same type of tester, a tester mayexperience a slight variation in delays from a different tester. In oneembodiment, the best case and the worst case timing delays are providedby the specification from the manufacturer.

The chip-load timing delay is considered in isolation from any timingdelays associated with the system and the tester. The delay shouldclosely approximate the delay of the fabricated chip and is calculatedat the chip-level in which every operational delay associated with eachinternal element (e.g., a transistor or a resistor) is included.Additionally, since different internal elements may be involved indifferent types of functions (e.g., executing an adding function versusa multiplication function), the time taken to perform one function mayvary from the time taken to perform a different function. Thus, thetiming delay associated with a first output state may be different fromthat of the next output state. The difference in delay from the firstoutput state to the next output state is the basis for an asynchronousvariability among the states.

Returning to FIG. 3, in step 82, short timing delays (hereinafter “shortdelays”) are introduced to the simulation sequence 68 of FIG. 2. In oneembodiment, the short delays are introduced to the simulation sequenceduring execution. Preferably, the short delays include a best case, or aminimum, tester-load timing delay and a best case, or a minimum,chip-load timing delay. Since each output state associated with the chipload is subject to a delay that may be different from a delayexperienced at a subsequent state in the sequence, the output sequenceis asynchronous. FIG. 4 shows an asynchronous short-delay sequence 84after introducing the short delays to the simulation sequence 68. Thesimulation sequence 68 of FIG. 4 is the same simulation sequence 68 ofFIG. 2B. In the asynchronous sequence 84, a cycle 88 is delayed by afirst delay 86 of 5 ns relative to the cycle 70 of the simulationsequence 68. A cycle 92 of the asynchronous sequence is delayed by asecond delay 90 of 10 ns relative to the corresponding cycle 70 of thesimulation sequence. Finally, a cycle 96 of the asynchronous sequence isdelayed by a third delay 94 of 5 ns relative to the corresponding cycle70 of the simulation sequence. Each delay 86, 90 and 94 includes acombined minimum delay of the chip and the tester. In an event in whicha delay has caused a state to cross a boundary into a next base period,the sequence may be shifted along the time domain, so that at least aportion of the crossed-over state is shifted back to its respective baseperiod. Alternatively, the crossed-over state may be masked to avoid afaulty sampling region. Most commercial testers provide for masking ofsampling regions by inserting a mask in the file sequence at a specifiedtime and location within the time domain.

In step 98 of FIG. 3, a time overlay is performed on every cycle 88, 92and 96 of the asynchronous short-delay sequence 84 of FIG. 4 forsynchronization. The step of overlaying is performed by time-aligningand correlating every base period 100. As a result, an overlapping(i.e., intersecting) cycle 102 is detectable. As shown, the overlappingcycle is an intersecting time interval of the cycles 88, 92 and 96within the cumulative base period. The overlapping cycle is indicated bydiagonal hatching in a downwardly direction from left to right. In anevent in which a cycle does not coincide with the overlapping cycle, thenon-overlapping cycle may be masked. While the overlaying step is shownas being performed for three base periods, in operation every baseperiod of the asynchronous sequence 84 is time-overlaid to identify theoverlapping cycle.

The clock period having the overlapping cycle 102 is duplicated in everybase period 100 in step 104 of FIG. 3. The duplicating step provides asynchronous short-delay sequence 106 of FIG. 4, where the overlappingcycle is repeated in every base period at the identical time location.

Independent of introducing the short delays to the simulation sequence68 in step 82 of FIG. 3, long timing delays (hereinafter “long delays”)are introduced to the simulation sequence in step 109. Preferably, thelong delays include a worst case, or a maximum, tester-load timing delayand a worst case, or a maximum, chip-load timing delay. FIG. 4 shows anasynchronous long-delay sequence 110 after introducing the long delaysto the simulation sequence 68. In the asynchronous sequence 110, a cycle114 is delayed by a first delay 112 of 15 ns relative to thecorresponding cycle 70 of the simulation sequence 68. A cycle 118 of theasynchronous sequence is delayed by a second delay 116 of 15 ns relativeto the corresponding cycle 70 of the simulation sequence. Finally, acycle 122 of the asynchronous sequence is delayed by a third delay 120of 10 ns relative to the cycle 70 of the simulation sequence. Each delay112, 116 and 120 is based on a combined maximum delay of the chip andthe tester. In an event in which a delay has caused a state to cross aboundary into a next base period, the sequence may be shifted so that atleast a portion of the crossed-over state is shifted back to itsrespective base period. Alternatively, the crossed-over state may bemasked to avoid a faulty sampling region.

Similar to the time overlaying step 98 of FIG. 3, a time overlaying step124 is performed for the base periods that contain the cycles 114, 118and 122 of the asynchronous long-delay sequence 110 of FIG. 4. The stepof overlaying is performed by time-aligning and correlating every baseperiod 126 to identify an overlapping (i.e., intersecting) cycle 128 ina cumulative period. The overlapping cycle is an intersecting timeinterval of the cycles 114, 118 and 122 within the base period 126. Thebase period 126 is equivalent in time to the base period 100.

The cumulative period having the overlapping cycle is duplicated inevery base period 126 in step 130 of FIG. 3. The duplicating stepprovides a synchronous long-delay sequence 132 in which the overlappingcycle is repeated in every successive period at the identical timelocation.

In step 136 of FIG. 3, a time overlay is performed on the synchronousshort-delay sequence 106 and the synchronous long-delay sequence 132 togenerate a synchronous sequence 138 of test vectors, as shown in FIG. 5.The synchronous short-delay sequence 106 and the long-delay sequence 132of FIG. 4 are the same sequences of FIG. 5. The step of overlaying isperformed by time aligning and correlating the synchronous sequences 106and 132 to identify successive overlapping cycles 140. The identifiedsuccessive overlapping cycles 140 is the synchronous sequence 138 oftest vectors. Each overlapping cycle 140 is an intersecting (i.e.,coinciding) time interval between a cycle 108 of the synchronoussequence 106 and a corresponding cycle 134 of the synchronous sequence132. The overlapping cycle is characterized by a rising edge thatcoincides with a rising edge of the cycle 134 and a falling edge thatcoincides with a falling edge of the cycle 108. Since the overlaying isperformed on the synchronous sequences 106 and 132, the resultingsequence 138 of test vectors is also synchronous.

Each overlapping cycle 140 of the synchronous sequence 138 of testvectors includes a time interval at which an output state can beproperly sampled by the tester. FIG. 6 shows an expanded view of theoverlapping cycle 140 of FIG. 5 within the base period 126. A samplinginstance 144 is fixed at a timing location within a timing interval 142of the cycle. The location of the sampling instance should correspond toa rising clock edge 149 of the tester cycle. The placement of thesampling instance should include a sufficient time interval 146 (i.e.,T_(setup)) before the sampling instance and a sufficient time interval148 (i.e., T_(hold)) after the sampling instance, but within the timinginterval, to ensure an adequate sampling of data by the tester. Theselection of the location of the sampling instance is repeated in everytester period such that the output data of the synchronous sequence oftest vectors will be sampled at substantially identical times andlocations in successive tester periods.

Returning to the flow diagram 80 of FIG. 3, step 150 is a step ofverifying the synchronous sequence 138 of test vectors to ensure thatthe sequence meets the timing constraints imposed by the loadcharacteristics of the system environment, the tester environment andchip environment. The verifying step is performed by executing thesynchronous sequence of test vectors to include the timing delaysassociated with the system environment, the best and worst casetester-load timing delays of the tester environment, and the best andworst case chip-load timing delays of the chip environment. An outputstate of the synchronous sequence 138 is sampled by the tester at eachsampling instance.

With reference to FIGS. 7 and 8, a system 160 for generating asynchronous sequence of test vectors from information originating withinan asynchronous environment is shown. An event-driven simulator 162 isconfigured to provide a simulated asynchronous sequence 16 of states forfunctionally verifying a simulated IC design under a system simulationenvironment. A recorder 164 records the simulated asynchronous sequenceinto a recording file, such as a Verilog Control Dump (VCD) file.

A synchronizer 166 synchronizes the simulated asynchronous sequence 16to generate the simulated synchronous sequence 44. The synchronizationis performed by extracting a state of the asynchronous sequence at eachbase period of a reference clock. Preferably, the time interval of thebase period is equivalent to the time interval of the tester clockperiod of the IC tester.

An abbreviated-delay module 168 introduces delays to the simulatedsynchronous sequence 44 to generate the simulated synchronousabbreviated-delay sequence 52. In one embodiment, the delay is theestimated best case, or a minimum timing delay, of the systemenvironment, excluding any delays associated with the chip and thetester. Independent of introducing the abbreviated timing delay to thesimulated synchronous sequence 44 by the module 168, an extended-delaymodule 170 introduces a longer timing delay to the simulated synchronoussequence to generate the simulated synchronous extended-delay sequence60. In one embodiment, the delay is the estimated worst case, or amaximum timing delay, of the system environment, excluding any delaysassociated with the chip and the tester.

A sequence overlaying module 172 is configured to perform a timingoverlay on the simulated synchronous abbreviated-delay sequence 52 andthe simulated synchronous extended-delay sequence 60 to generate thesimulation (synchronous) sequence 68. The overlaying is performed bytime-aligning and correlating the sequences 52 and 60 to identifyintersecting time intervals. Since delays associated with the tester andthe chip have not been considered, the simulation sequence 68 onlyprovides delays associated with the system environment.

In FIG. 8, a short-delay module 174 is configured to introduce shorttiming delays to the simulation sequence 68 of FIG. 7 to generate theasynchronous short-delay sequence 84. In one embodiment, theshort-delays include a best case, or a minimum, tester-load timing delayand a best case, or minimum, chip-load timing delay. The sequence 84 isasynchronous, since a chip-load timing delay that is associated with anoutput state may be different from the delay of a next output state.This may be due to a variability in the time taken to perform differentfunctions of the chip. A cycle overlaying module 176 is enabled toperform a timing overlay on every cycle of the asynchronous short-delaysequence 84 to provide an overlapping (i.e., intersecting) time cycle102. The clock period having the overlapping cycle is duplicated by aduplication module 178 to generate the synchronous short-delay sequence106.

Similar to, but independent of, introducing the short timing delays tothe simulation sequence 68 by the short-delay module 174, a long-delaymodule 180 is configured to introduce long timing delays to thesimulation sequence 68 to generate the asynchronous long-delay sequence110. In one embodiment, the long delays include a worst case, or amaximum, tester-load timing delay and a worst case, or maximum,chip-load timing delay. A cycle overlaying module 182 is enabled toperform a timing overlay on every cycle of the asynchronous long-delaysequence 110 to provide an overlapping (i.e., intersecting) time cycle128. The clock period having the overlapping cycle is duplicated by aduplication module 184 to generate the synchronous long-delay sequence132.

A sequence overlaying module 186 is configured to perform a timingoverlay for the synchronous short-delay sequence 106 and the synchronouslong-delay sequence 132 to generate a stream of intersecting timeintervals that defines the synchronous sequence 138 of test vectors. Averification module 188 verifies the synchronous sequence 138 to ensurethat it meets the timing constraints imposed by the system environment,tester environment and chip environment.

While the cycle overlaying modules 176 and 182 are shown as distinctmodules, the functions performed by the two modules can be performed bya single cycle overlaying module, typically a software module, withoutdiverging from the scope of the invention. Similarly, the functionsperformed by the duplication modules 178 and 184 can be performed by asingle software and/or hardware duplication module. Moreover, thefunctions performed by respective sequence overlaying modules 172 ofFIG. 7 and 186 of FIG. 8 can be performed by a single sequenceoverlaying module.

1. A computer-implemented method of driving the simulation testing of adesign of an integrated circuit (IC) which is to be incorporated into anintended system comprising the steps of: providing an asynchronoussequence of states configured for simulating operating conditionsrelevant to driving sequencing of signal-exchange events with said IC;identifying first upper and first lower parameters of timing constraintsimposed by said intended system with respect to enabling individual saidevents; forming a first synchronous sequence of states in which saidstates are synchronized on a basis of remaining within said first upperand first lower parameters of timing constraints; identifying secondupper and second lower parameters of timing constraints imposed by saidIC with respect to enabling individual said events; forming a secondsynchronous sequence of states in which said states are synchronized ona basis of remaining within said second upper and said second lowerparameters of timing constraints; and using said second synchronoussequence as a basis for said simulation testing of said design.
 2. Acomputer-implemented method of generating a synchronous sequence of testvectors from information originating within an asynchronous environmentcomprising: providing a simulation synchronous sequence of states,wherein each of said states is referenced to a clock period, saidsimulation synchronous sequence being partially based on event timingparameters of a particular system of interest; introducing short timingdelays to said states within specific said clock periods of saidsimulation synchronous sequence to generate an asynchronous short-delaysequence of states, durations of specific said short timing delays beingresponsive to event timing parameters of a particular integrated circuit(IC) design; comparing said states of said asynchronous short-delaysequence, including correlating a plurality of said clock periods havingsaid states of said asynchronous short-delay sequence to identify afirst over-lapping time interval, said first overlapping time intervalbeing consistent with a time coincidence among said states of saidasynchronous short-delay sequence; generating a synchronous short-delaysequence by successively repeating a first delay-adjusted clock periodhaving a state which is delayed by said first overlapping time interval;introducing long timing delays to said states within specific said clockperiods of said simulation synchronous sequence to generate anasynchronous long-delay sequence of states, durations of specific saidlong timing delays being responsive to event timing parameters of saidparticular IC design; comparing said states of said asynchronouslong-delay sequence, including correlating a plurality of said clockperiods having said states of said asynchronous long-delay sequence toidentify a second overlapping time interval, said second overlappingtime interval being consistent with a time coincidence among said statesof said asynchronous long-delay sequence; generating a synchronouslong-delay sequence by successively repeating a second delay-adjustedclock period having a state which is delayed by said second overlappingtime interval; and comparing said synchronous short-delay sequence withtiming of said states of said synchronous long-delay sequence togenerate said synchronous sequence of test vectors, including timealigning said synchronous short-delay and long-delay sequences to detecta plurality of overlapping sampling time intervals for locating saidsynchronous sequence of test vectors.
 3. The computer-implemented methodof claim 2 wherein said step of introducing said short timing delaysincludes adding best case tester-load timing delays to said clockperiods of said simulation synchronous sequence, said best casetester-load timing delays being indicative timing constraints of an ICtester.
 4. The computer-implemented method of claim 3 wherein said stepof introducing said long timing delays includes adding worst casetester-load timing delays that are indicative of said timing constraintsof said IC tester.
 5. The computer-implemented method of claim 2 whereinsaid step of introducing said short timing delays includes adding bestcase chip-load timing delays indicative of timing constraints of said ICdesign.
 6. The computer-implemented method of claim 5 wherein said stepof introducing said long timing delays includes adding worst casechip-load timing delays indicative of said timing constraints of said ICdesign.
 7. The computer-implemented method of claim 2 wherein said stepof providing said simulation synchronous sequence includes: providing asimulated asynchronous sequence of states; extracting a state of saidasynchronous sequence at each said clock period to generate a simulatedsynchronous sequence of states; introducing an abbreviated liming delayto each said clock period of said simulated synchronous sequence togenerate a simulated synchronous abbreviated-delay sequence andintroducing an extended timing delay to each said clock period of saidsimulated synchronous sequence to generate a simulated synchronousextended-delay sequence; and comparing said simulated synchronousabbreviated-delay sequence to said simulated synchronous extended-delaysequence, including time aligning said simulated synchronousabbreviated-delay and extended-delay sequences to detect a plurality ofoverlapping second time intervals for defining positions of states insaid clock periods of said simulation synchronous sequence.
 8. Thecomputer-implemented method of claim 7 wherein said step of introducingsaid abbreviated timing delay and said extended timing delay includesexecuting said simulated synchronous sequence under respective best casetiming delay and worst case timing delay scenarios in a systemsimulation environment, said system simulation environment having timingcharacteristics indicative of said particular system of interest.
 9. Thecomputer-implemented method of claim 7 further including adapting saidsimulated synchronous extended-delay sequence as said simulationsynchronous sequence when there is not an acceptable number of saidoverlapping second time intervals.
 10. The computer-implemented methodof claim 7 wherein said step of providing said simulated asynchronoussequence includes selecting said clock period to have a duration thatcorresponds to a tester clock period of an IC tester.
 11. Thecomputer-implemented method of claim 2 further including selectivelyfixing a sampling instance in one of said overlapping sampling timeintervals to correspond to a rising edge of a tester clock period of anIC tester.
 12. A test vector generator for generating a synchronoussequence of test vectors comprising: a computer-implemented simulationmodule that is enabled to generate a simulation synchronous sequence ofstates under a system simulation environment, said simulationsynchronous sequence including a plurality of timing regions foridentifying operations of an integrated circuit (IC) design; acomputer-implemented delay module that is enabled to introduce shortdelays and long delays to said simulation synchronous sequence torespectively generate asynchronous short-delay sequence and asynchronouslong-delay sequence, each of said short delays and said long delaysbeing timing delays associated with at least one of an integratedcircuit (IC) and an IC tester; a computer-implemented overlaying modulethat is configured to provide a first state overlapping time intervaland a second state overlapping time interval by respectively comparing aplurality of base periods of said asynchronous short-delay sequence andcomparing a plurality of base periods of said asynchronous long-delaysequence; a computer-implemented duplication module that is configuredto incorporate said first state overlapping time interval into a firstsequence of said base periods and to incorporate said second stateoverlapping time interval into a second sequence of said base periods torespectively generate a synchronous short-delay sequence and asynchronous long-delay sequence; and a computer-implemented sequenceoverlaying module that is configured to time align said synchronousshort-delay sequence and said synchronous long-delay sequence to detecta plurality of overlapping sampling intervals for locating saidsynchronous sequence of test vectors.
 13. The test vector generator ofclaim 12 wherein said short delays are related to a best case chip-loadtiming delay of said IC and a best case tester-load timing delay of saidIC tester.
 14. The test vector generator of claim 13 wherein said longdelays are related to a worst case chip-load timing delay of said IC anda worst case tester-load timing delay of said IC tester.
 15. The testvector generator of claim 12 further comprising a computer-implementedverification module that is configured to execute said synchronoussequence of test vectors under said short delays and said long delaysfor verifying timing correctness.
 16. The test vector generator of claim12 wherein said system simulation environment is independent of anydelay associated with said IC and said IC tester.
 17. The test vectorgenerator of claim 12 wherein said base period is a time interval thatis equivalent to a tester period of said IC tester.
 18. Acomputer-implemented method for converting asynchronous states intosynchronous states to generate a synchronous sequence of test vectorsfor verifying functionality of a simulated integrated circuit (IC)design comprising: providing a simulation synchronous sequence ofstates; generating an asynchronous short-delay sequence of first periodsand an asynchronous long-delay sequence of second periods, includinginserting short delays and long delays into said simulation synchronoussequence, said short delays and said long delays characterizing timingdelays of at least one of said simulated IC and a tester; detecting ashort-delay overlapping time interval and a long-delay overlapping timeinterval, including correlating a plurality of said first periods toidentify said short-delay overlapping time interval and correlating aplurality of said second periods to identify said long-delay overlappingtime interval; generating a synchronous short-delay sequence of statesby forming a succession of substantially identical base periods thatinclude a state and said short-delay overlapping time interval;generating a synchronous long-delay sequence of states by forming asuccession of substantially identical base periods that include a stateand said long-delay overlapping time interval; and generating saidsynchronous sequence of test vectors, including time-aligning saidsynchronous short-delay sequence and said synchronous long-delaysequence and identifying overlapping timing envelopes of states withincorresponding said base periods of said synchronous short-delay andlong-delay sequences.
 19. The computer-implemented method of claim 18wherein said step of inserting said short delays and said long delaysincludes respectively introducing best-case timing delays of saidsimulated IC and worst-case timing delays of said simulated IC.
 20. Thecomputer-implemented method of claim 19 wherein said step of insertingsaid short delays and said long delays includes respectively introducingbest-case timing delays of said tester and worst-case timing delays ofsaid tester.